Planar dual gate semiconductor device

ABSTRACT

A method of fabricating a dual-gate semiconductor device is provided in which silicidation of the source and drain contact regions ( 34, 36 ) is carried out after the first gate ( 12 ) is formed on part of a first surface ( 14 ) of a silicon body ( 16 ) but before forming a second gate ( 52 ) on a second surface ( 44 ) of the silicon body which is opposite the first surface. The first gate ( 12 ) serves as a mask to ensure that the silicided source and drain contact regions are aligned with the silicon channel ( 18 ). Moreover, by carrying out the silicidation at an early stage in the fabrication, the choice of material for the second gate is not limited by any high-temperature processes. Advantageously, the difference in material properties at the second surface of the silicon body resulting from silicidation enables the second gate to be aligned laterally between the silicide source and drain contact regions.

The invention relates to a dual-gate semiconductor device having asilicon body which comprises a channel and source and drain contactregions separated laterally by the channel.

The desire for smaller and more compact electronic devices in today'selectronics market presents the challenge to manufacturers to providesmaller and more compact integrated circuits (ICs) and othersemiconductor devices. Metal-oxide-semiconductor field-effecttransistors (MOSFETs) are primary components of most ICs and, therefore,occupy a significant amount of wafer space. Reducing the size of MOSFETsin ICs, for sub-50 nm CMOS applications for example, plays a significantrole in meeting the size-reduction challenge.

Several problems are associated with reducing the size of transistordevices. For example, short-channel effects are more likely to becomeapparent when the length of the conduction channel is made shorter.These effects are caused by the extension of the depletion region of thedrain into the channel under the influence of a voltage on the drain. Tosuppress short-channel effects it is known to provide a transistorstructure having more than one gate. Each gate is arranged to controlthe conduction of the channel by applying a voltage thereto from morethan one direction.

An example of such a structure is the planar dual-gated MOSFET which hastwo gates that are positioned on opposite surfaces of a semiconductorbody comprising the channel, separated therefrom by respective gatedielectrics. Without accurate alignment of the gates with each other,short-channel effects can result in inferior device performance.Moreover, any undesirable overlap between the gates and the channel maycause increased capacitances leading to reduced device speed. Suchalignment errors are compounded by any reduction in device size.Therefore, accurate alignment of the gates with respect to the channeland with each other becomes critical to device performance for smallMOSFETs, for example with those having gate lengths <100nm.

U.S. Pat. No. 6,593,192 discloses an example method of forming adual-gate semiconductor-on-insulator (SOI) device in which a first gateis aligned with a second gate, each being formed on opposing sides of asemiconductor layer. In this, first gate structures are formed overactive areas before a masking layer is deposited and patterned to exposeregions of the semiconductor layer not covered by the first gatestructures. Contact openings are then etched through source and drainregions and into an underlying insulator layer via windows in themasking layer. The contact openings are then filled with a conductivematerial to form source and drain contact structures. A handle wafer isbonded to the upper surface of the structure and the bulk substrate isremoved to expose the insulator layer as well as the source and draincontact structures. As shown in FIG. 8 of U.S. Pat. No. 6,593,192,portions of the insulator layer 20 are removed to form openings 26between adjacent source and drain contact structures 58. Such removalcan be accomplished by depositing a masking layer and patterning thelayer to expose the desired areas of layer 20 which are then etched byan appropriate etching process that selectively removes the material oflayer 20 and not the material of the contact structures 58. Secondtransistor gate structures 95 are then formed within the openings 26, asshown in FIG. 9 of U.S. Pat. No. 6,593,192.

The second gate structures are self-aligned to the first transistor gatestructures 45 and to the channel region therebetween. The source anddrain contact structures 58 provide for the alignment of the first andsecond transistor gate structures. However, in order to form the deepsource and drain contact structures in the device described in U.S. Pat.No. 6,593,192, several processing steps are necessary to ensure that thestructures are aligned to the channel regions.

It is an object of the present invention to provide an improved methodof fabricating a dual-gate semiconductor device.

It is another object of the present invention to provide a method offabricating a dual-gate semiconductor device having fewer processingsteps to that disclosed in U.S. Pat. No. 6,593,192.

According to the present invention there is provided a method offabricating a dual-gate semiconductor device having a silicon body whichcomprises a channel and source and drain contact regions separatedlaterally by the channel, the method comprising the steps of, forming afirst gate on part of a first surface of a silicon body, therebydefining a channel in the silicon body under the first gate, silicidingregions of the silicon body not covered by the first gate, so as todefine silicide source and drain contact regions, and then, forming asecond gate on a second surface of the silicon body which is oppositethe first surface, wherein the second gate is aligned laterally betweenthe silicide source and drain contact regions.

By siliciding the source and drain contact regions before the formationof the second gate, the difference between the material of the sourceand drain and the silicon body at the second surface can be exploited toalign the second gate with the first gate. Advantageously, thesiliciding process does not require the masking layer needed by themethod taught by U.S. Pat. No. 6,593,192 to etch deep contact openings.In fact, the first gate serves as a mask during silicidation of thesilicon body. Therefore, the silicided source and drain contact regionsare inherently self aligned with the first gate. This reduction in thenumber of required process steps provides for a faster, and thereforecheaper, fabrication flow.

The silicidation is carried out before the formation of the second gate.Therefore, the relatively high temperature range associated withsilicidation does not limit the choice of material used for the secondgate and, thereby, provides a more flexible process.

In a preferred embodiment, the second gate is formed in a recess whichis formed in the second surface between the silicide source and draincontact regions. The recess can be formed simply by selectively etching,from the second surface, a portion of the silicon between the silicidesource and drain contact regions. Such selective etching is enabled bythe difference in properties of the silicided source/drain contacts andthe silicon body portion at the second surface (remote from the firstgate). For example, the second surface of the silicon body can beoxidised. The silicide source/drain contacts will not become oxidisedwhich allows the oxidised silicon to be selectively etched to form therecess. Preferably, insulating spacers are formed within the recessbefore forming the second gate to prevent contact between the secondgate and the silicide source and/or drain contact regions.

Spacers may be formed adjacent the first gate on the first surfacebefore the silicide source and drain contact regions are defined. Thesespacers are employed to mask off regions of the silicon body so thatdopant can be implanted through an exposed part of the first surface soas to define junction regions adjacent the channel.

The invention will now be described, by way of example only, withreference to the accompanying drawings wherein;

FIGS. 1 to 5 show sectional views of a dual-gate semiconductor device atvarious stages of manufacture according to a first embodiment of theinvention; and,

FIG. 6 shows a sectional view of a dual-gate semiconductor devicefabricated according to a second embodiment of the invention.

It will be appreciated that the figures are merely schematic and are notdrawn to scale. In particular certain dimensions such as the thicknessof layers or regions may have been exaggerated whilst other dimensionsmay have been reduced. The same reference numerals are used throughoutthe figures to indicate the same or similar parts.

An example embodiment of a method of fabricating a dual-gatesemiconductor device according to the invention will now be describedwith reference to FIGS. 1 to 5. It should be appreciated by the skilledperson that various known semiconductor processing techniques can beemployed in the following described method to deposit, pattern, etch anddope various conducting, insulating and semiconductor structures on asilicon wafer. For example, low pressure chemical vapour definition(LPCVD) may be used to deposit conductive layers which can besubsequently patterned as required.

A first gate 12 is formed on part of a first surface 14 of a siliconbody 16, thereby defining a channel 18 in the silicon body under thefirst gate, as shown in FIG. 1. The silicon body 16 is bonded to aninsulating layer 20 which is supported by a first substrate 22 therebyforming a silicon-on-insulator (SOI) wafer 24 in which the insulatinglayer 20 is of silicon oxide for example. This insulating layer iscommonly referred to as the buried oxide of the SOI wafer. The siliconbody is thinned down using sequential silicon oxidation and wet etchingof the oxide to a thickness of 30-60 nm , typically 40 nm.

Before the first gate 12 is formed, isolation regions 26 must be formedin the silicon body 16. These serve to prevent electrical interferencebetween neighbouring semiconductor devices on the same wafer and areformed using known techniques such as shallow trench isolation. A gateinsulating layer of silicon oxide or high-K is then grown or depositedto provide a gate dielectric 28 for the first gate 12.

As an alternative to shallow trench isolation, local oxidation ofsilicon (LOCOS) could be employed to isolate adjacent active regions.Since the silicon body sufficiently thin, only a thin oxidation would beneeded if LOCOS is used. This will ensure small lateral extension of theLOCOS oxide into the active region, a so-called “Birdsbeak”. Anotherprocessing option would be to simply etch mesas, or islands, of siliconisolated by the buried oxide (BOX).

A polycrystalline silicon (polysilicon) layer is then deposited on thegate insulating layer. This is patterned and etched together with thegate insulating layer to define the first gate 12 which is separatedfrom the silicon channel 18 by the gate dielectric 28. Alternatively,metal, or any other highly-conductive material, electrode can be used toform the gate.

Doped junction regions 30 are then defined in the silicon body 16laterally spaced by the channel 18. This definition process requiresforming a pair or spacers 32, formed of oxide, nitride or a combinationof both, each side adjacent the first gate 12 on the first surface 14 ofthe silicon body. The spacers 32 have dimensions of approximately 45 nm. Dopant, n-type (e.g. As or P) for NMOS, or p-type (B or In) for PMOS,is then implanted through the exposed part of the first surface 14 ofthe silicon body 16. This is activated by heating. Normally a very shortduration of <1second at the peak temperature, so-called “spike” RapidThermal Annealing (RTA) is used, with very high ramp up and ramp downrates (above 100°/s). This, as a consequence, causes the dopant todiffuse partly under the spacers 32 but not into the channel 18.

With reference to FIG. 2, common CMOS self-aligned silicidationprocessing is then used to silicide regions of the silicon body 16 notcovered by the first gate 12, so as to define silicide source and draincontact regions 34, 36. This siliciding process involves depositing alayer of metal, nickel, cobalt or titanium for example, over the firstsurface 14. This is then heated by RTA to temperatures of approximately380-450° C. so as to anneal the nickel to form silicide source and draincontact regions 34, 36 in the silicon body thereunder. The remainingnickel layer, (that which has not reacted with the underlying silicon)is then removed from the first surface 14.

Alternatively, cobalt or titanium, for example, may be used instead ofnickel. For Cobalt, the temperature to form the silicide is around 700°C. and for Titanium a temperature of around 850° C. is required.

As well as the source and drain contact regions 34, 36, the first gate12 is exposed to the silicidation process and, therefore, becomessilicided.

During the silicidation process the first gate 12 and insulating spacers32 serve as a natural mask which means that the silicide source anddrain contact regions 34, 36 are inherently self-aligned with the firstgate 12. Moreover, the presence of the insulating spacers 32 ensuresthat bridging between the silicided regions is avoided.

The silicide is formed through the thickness of the silicon body down tothe buried oxide 20. The thickness and any lateral extension of thesilicide depends on the amount of nickel deposited and the thickness ofthe silicon layer. If a large amount of nickel is deposited, thesilicide may extend underneath the spacer as shown. Advantageously, thisreduces the series resistance of the device.

An amorphisation implant (not shown) can be carried out to amorphize thesource and drain contact regions 34, 36 before silicidation. Thesilicidation process is typically faster in amorphized silicon than incrystalline silicon. Therefore, by choosing an appropriate thermalbudget, the silicide can be blocked to stop it crossing the interfacewith the channel.

The silicon channel 18, together with doped junction regions, is definedbetween the laterally spaced silicide source and drain contact regions34, 36. Due to the inherent self-alignment of the source and draincontact regions, the channel is aligned with the overlying first gatestack.

With reference to FIG. 3, a second wafer is bonded to the structureshown in FIG. 2 by oxide fusion bonding. In this, a second insulatinglayer of silicon oxide 40 serves to bond a second substrate 42 to thefirst gate 12 and the exposed part of the first surface 14 of thesilicon body 16. This second wafer 40,42 is commonly referred to as ahandling wafer because it facilitates handling of the semiconductordevice whilst the first wafer is removed for processing of the oppositeside of the silicon body 16 (backside processing).

Once the second wafer is bonded to the silicon body, the first substrate22 and the insulating layer 20 are removed so as to expose the secondsurface 44 of the silicon body 16. This removal can be carried out by achemical wet etch or grinding or a combination of both.

FIG. 4 shows the semiconductor device after removal of the firstsubstrate and the insulating layer and after the whole structure hasbeen turned upside-down for backside processing.

The then-exposed second surface 44 of the silicon body 16 is subjectedto an oxidation process. This serves to oxidise the silicon of thechannel 18 to a depth of approximately 60 nm but not the silicide sourceand drain contacts 34, 36.

A selective etch is then carried out to remove the oxidised silicon toform a recess in the second surface 44 between the silicide source anddrain contact regions 34, 36. For example a buffered oxide etch (BOE)can be used to remove the oxide. The recess formed is aligned with thefirst gate and the silicon channel because the extent of the selectiveetch is limited by the sidewalls of the silicide source and draincontacts. Following the selective etch, a portion of the silicon bodyopposite the first gate 12 remains. This remaining portion forms theconduction channel 18 for the final device and which channel is alignedwith the first gate 12 and the recess.

Advantageously, the thickness of the channel 18 can be easily controlledby the extent to which the exposed second surface 44 of the silicon body16 is oxidised during the oxidation step. Typically, the thickness ofthe channel is 10 nm and the thickness of the silicide source and draincontact regions 34, 36 remains at 40-50 nm . The thicker source anddrain ensures that the device has a low series resistance whilst thethin channel, having a well-controlled thickness, is fully controllableby the gates, resulting in a device having appropriate transistorcharacteristics.

A gate insulator layer, of silicon oxide for example, is deposited overthe second surface of the silicon body 16. This is then patterned toform a gate dielectric 48 within the recess. A second gate 52 is thenformed on the second surface of the silicon body by depositing a layerof polysilicon or metal over the second surface and patterning. It willbe appreciated, however, that a conductive material other thanpolysilicon could be used to form the second gate 52. By carrying outthe silicidation before the formation of this second gate stack, themelting temperature of the material does not limit the choice.

The second gate 52 is aligned laterally between the silicide source anddrain contact regions 34, 36. This ensures that the second gate is alsoaligned with the first gate 12 and the channel 18 thereby providing adual-gate semiconductor device having desirable electricalcharacteristics.

The gate dielectric 48, as shown in FIG. 5, provides insulation betweenthe second gate 52 and the silicide source and drain contact regions 34,36, as well as the channel 18. However, to improve the insulation andreduce any risk of shorting due to poor step coverage, insulatingspacers 55 can be formed within the recess before forming the secondgate, as shown in FIG. 6. The spacers can also serve to reduce overlapbetween the second gate and the junction regions 30 which could causeunwanted capacitative effects.

The thickness of the second gate 52 is determined by the depth of therecess in the second surface 44. It will be appreciated by the skilledperson, however, that this thickness can be more or less than the depthof the recess by appropriate processing.

Although it is envisaged that oxidation is performed on the secondsurface 44 of the silicon body before selectively etching the recess, itwill be appreciated that other etching techniques could be adopted. Thisis possible because the exposed second surface after removal of theinsulating layer 20 comprises two different materials, the silicide ofthe source and drain contact regions 34, 36, and the silicon oppositethe first gate 12. For example, the silicon can be directly etched awayselectively towards the silicide regions, thereby forming a recesswithout oxidation.

Despite the clear advantages of providing a self-aligned recess forforming the second gate stack therein, it is envisaged that thedifference in material properties on the second surface could allow thesecond gate stack (dielectric and gate) to be formed directly thereonwithout forming a recess. For example, the conditions used during thesilicidation process could be adapted to cause the silicide source anddrain contact regions 34, 36 to protrude from the second surface 44 by asmall amount beyond the unaffected silicon. Such protrusion is effectedby the natural gain in volume that silicon undergoes when converted tosilicide. This would effectively form small steps in the second surface,at the interface between the different materials, which can beadvantageously exploited to align the second gate 52 with the first gate12.

In summary, with reference to FIG. 5, there is provided a method offabricating a dual-gate semiconductor device in which silicidation ofthe source and drain contact regions 34, 36 is carried out after thefirst gate 12 is formed on part of a first surface 14 of a silicon body16, but before forming a second gate 52 on a second surface 44 of thesilicon body, which is opposite the first surface. The first gate 12serves as a mask to ensure that the silicided source and drain contactregions are aligned with the silicon channel 18. Moreover, by carryingout the silicidation at an early stage in the fabrication, the choice ofmaterial for the second gate is not limited by any high-temperatureprocesses. Advantageously, the difference in material properties at thesecond surface of the silicon body resulting from silicidation enablesthe second gate to be aligned laterally between the silicide source anddrain contact regions.

From reading the present disclosure, other modifications will beapparent to persons skilled in the art. Such modifications may involveother features which are already known in the design, manufacture anduse of dual-gate semiconductor devices and component parts thereof, andwhich may be used instead of or in addition to features alreadydescribed herein. Although claims have been formulated in thisapplication to particular combinations of features, it should beunderstood that the scope of the disclosure of the present applicationalso includes any novel feature or any novel combination of featuresdisclosed herein either explicitly or implicitly or any generalisationthereof, whether or not it relates to the same invention as presentlyclaimed in any claim and whether or not it mitigates any or all of thesame technical problems as does the present invention. The applicantshereby give notice that new claims may be formulated to such featuresand/or combinations of features during the prosecution of the presentapplication or of any further application derived therefrom.

1. A method of fabricating a dual-gate semiconductor device having asilicon body which comprises a channel and source and drain contactregions separated laterally by the channel, the method comprising thesteps of: forming a first gate on part of a first surface of a siliconbody, thereby defining a channel in the silicon body under the firstgate; siliciding regions of the silicon body not covered by the firstgate, so as to define silicide source and drain contact regions andthen, forming a second gate on a second surface of the silicon bodywhich is opposite the first surface, wherein the second gate is alignedlaterally between the silicide source and drain contact regions.
 2. Amethod according to claim 1, further comprising the step of: forming arecess in the second surface between the silicide source and draincontact regions before the second gate is formed, wherein the secondgate is formed in the recess.
 3. A method according to claim 2, whereinthe recess is formed by selectively etching, from the second surface, aportion of the silicon between the silicide source and drain contactregions.
 4. A method according to claim 3, further comprising the stepof: oxidising the second surface before selectively etching.
 5. A methodaccording claim 2, further comprising the step of: forming at least oneinsulating spacer within the recess before forming the second gate toprevent contact between the second gate and the silicide source and/ordrain contact regions.
 6. A method according to claim 1, wherein thesecond surface of the silicon body is initially bonded to an insulatinglayer which is supported by a first substrate.
 7. A method according toclaim 6, further comprising the steps of: bonding a second substrate tothe first gate and the first surface of the silicon body after thesilicide source and drain contact regions are defined; and then,removing the first substrate and the insulating layer so as to exposethe second surface of the silicon body.
 8. A method according to claim1, further comprising the steps of: forming at least one spacer adjacentthe first gate on the first surface (14); and then, implanting dopantthrough an exposed part of the first surface so as to define junctionregions adjacent the channel before the silicide source and draincontact regions are defined.
 9. A method according to claim 1, whereinthe siliciding includes the steps of: depositing a metal layer over thefirst surface; annealing the metal layer so as to form silicide sourceand drain contact regions thereunder; and then, removing the metal layerfrom the first surface.